1. Technical Field
The present invention relates to measurement and compensation circuits, and more particularly to methods and circuits, which measure and compensate for static phase error in phase locked loops.
2. Description of the Related Art
Phase locked loops (PLLs) are used in many integrated circuits to distribute and multiply clock signals while maintaining a constant phase (timing relationship) with respect to a reference clock. Basic blocks of PLLs are illustratively shown in FIG. 1A.
Referring to FIG. 1A, a phase locked loop (PLL) circuit 10 includes a phase and frequency detector (PFD) 12 at the input. At this point, (at PFD 12) a reference clock 14 and a feedback clock 16 generated by the PLL should have the same phase, that is, they should arrive at the same time. However, because of circuit design or process problems, it is possible that these signals may not be in phase, that is, that there is an average difference in timing at this point, which is known as a static phase error. The PFD 12 outputs a signal which indicates whether the reference clock and the feedback clock are out of phase. This output signal activates a charge pump 17 to generate a voltage on the capacitor 18 of the loop filter 20, which controls the frequency of the voltage controlled oscillator 24.
In particular, leakage through a capacitor 18 of a loop filter 20, which is an increasing problem in modern semiconductor processing technologies, can cause static phase error even though the rest of the PLL functions correctly. A voltage controlled oscillator (VCO) 24 outputs a clock signal 26. This clock signal is used for feedback through a frequency divider 28 to become the feedback clock 16, which is compared to the reference clock 16.
The result of static phase error is shown in FIG. 1B. Referring to FIG. 1B, the phase of the reference clock 14 and the average phase of the feedback clock 16 differ. The feedback clock 16 also has some jitter, as shown. A static phase error 30 corresponds to the mean value of the jittery feedback clock.
Static phase error must be kept below some minimum specified value. Excessive phase error will increase the jitter, and reduce the frequency operating range of the PLL. However, there is no easy way to measure it, and no way to correct it if it is out of range of the specification. At present, it can be measured only by bringing the signals off chip through high bandwidth driver input/output devices, connection via high bandwidth cables, and using an oscilloscope for the measurements.